In a typical digital wireless communication system, a transmitter in a transmitting communication device receives an input of digital information, such as a bit stream, from a data source. The bit stream is provided to a symbol mapper that groups the bit stream into groups of multiple bits and maps each group of multiple bits to a corresponding symbol to produce a symbol stream. To this end, a signal constellation that includes M possible symbols is defined within a multi-dimensional space, preferably a complex two-dimensional (I,Q) space. Each symbol comprises a point within the two-dimensional space, which point may be thought of as a vector sum of two scaled basis vectors. In order to achieve the desired mapping, the symbol mapper assembles the bits into groups of multiple bits. Each group of multiple bits is then used to select a symbol out of the M possible symbols. Many modulation schemes exist for mapping each bit group to a symbol, including multiple phase shift keying (MPSK) modulation schemes, such as BPSK or QPSK, and multiple quadrature amplitude modulation (MQAM) schemes, such as 16-QAM and 64-QAM. The transmitter converts the symbols to analog signals, modulates the analog signals onto a carrier, and transmits the analog carrier.
A receiver in a receiving communication device receives the transmitted signal, demodulates the received signal, and samples the demodulated signal in order to reproduce the transmitted symbols. Ideally, each sampled symbol should map to one of the M defined symbols in the modulation scheme. However, many intervening factors can cause the samples to map to points in the complex two-dimensional (I,Q) space other than the points corresponding to the M defined symbols. One such factor is system timing errors. A difference between a clock frequency of a transmitter and a clock frequency of a receiver can cause a constant drift in a time reference of the receiver with respect to the transmitter. In addition, phase jitter in the received signal also contributes to timing errors with respect to the received signal. A result of the time reference differential and the phase jitter is a sampling of the received signal at a point other than the optimal sampling point. When the received signal is sampled at other than the optimal point, the received signal may be mapped to a point that is offset from the points corresponding to the M defined symbols. Results of sub-optimal sampling include data translation errors and degradation in the signal-to-noise ratio (SNR) of the receiver.
In order to address the problem of timing errors, timing recovery circuits have been proposed. One such circuit is proposed in U.S. Pat. No. 6,055,284, “Symbol timing Recovery Circuit in Digital Demodulator”(hereinafter referred to as the “'284” patent). The '284 patent proposes a timing recovery circuit that includes a signal switch, or sampling means, for sampling a received signal, an interpolator that interpolates the sampled signal in an interpolation interval, and a data filter that that filters the interpolated signal to produce strobe data. All interpolating is performed by the interpolator, which includes an “L” sample, or tap, long delay line and corresponding “L” tap coefficients. The timing recovery circuit of the '284 patent further includes a feedback loop that includes a timing error detector, a loop filter, and a controller. The controller includes a fraction extractor that outputs a fractional interval, based on a sampled signal, to a filter tap-coefficient calculator that is included in the interpolator. The filter tap-coefficient calculator then recalculates all “L” tap coefficients based on the fractional interval in order to adjust and synchronize the sampling of the received signal in the next sampling period.
A drawback to the timing recovery circuit of the '284 patent is a processing load imposed by the circuit for each sampling period. All interpolation coefficients are recalculated in each sampling period, which can be a significant number of coefficients. Furthermore, a Rake receiver used in a code division multiple access (CDMA) communication system includes multiple received signal demodulators. Ideally, each demodulator is assigned to a single resolvable multipath component of a transmitted signal. Implementation of the '284 patent in a Rake receiver would require a separate interpolator for each demodulator to synchronize the signal received by that demodulator with the transmitted signal, greatly multiplying the complexity and processing load imposed upon the receiving communication device by the multiple timing recovery circuits.
In addition, second generation IS-95 systems employ data rates of less than 14.4 kilobits per second (kbps) and use low order modulation schemes such as BPSK or QPSK. Such slower data rates and low order modulation schemes tolerate lower SNR's and greater timing errors than the high data third-generation IS-95 systems, which have data rates of up to 5 megabits per second (Mbps) and require a higher order modulation schemes such as 16-QAM or 64-QAM. As a result, a typical second generation system employs a simple timing recovery circuit that tolerates timing errors of {fraction (1/16)} chip or more and uses a first order delay locked loop. Such a system is inadequate for a third generation system, where a timing error of just {fraction (1/32)} chip can lead to a SNR degradation of over 3 decibels (dB), which is intolerable for many high order modulation schemes.
Therefore, a need exists for a method and apparatus for receiving data that introduces a reduced processing load and a reduced timing error relative to current timing recovery circuits.